The invention relates to semiconductor processing, and more particularly to an improved method for forming a buried plate and a collar such as in the fabrication of a trench capacitor of an advanced microelectronic device, e.g., a dynamic random access memory (DRAM).
A goal of the semiconductor industry is to increase the circuit density of integrated circuits (“ICs” or “chips”), most often by decreasing the size of individual devices and circuit elements of a chip. Trench capacitors are used in some types of DRAMs for storing data bits. Often, increasing the circuit density of such DRAMs requires reducing the size of the trench capacitor, which, in turn, requires reducing the area of the chip occupied by the trench capacitor. Achieving such reduction in surface area is not straightforward, because different components of the storage capacitor do not scale at the same rate, and some components cannot be scaled below a certain size.
One problem of conventional fabrication techniques is that the buried plate of the trench capacitor is formed in a processing step which is separate from that in which a collar is formed above the buried plate. Because of this, the trench capacitor has lower than desired capacitance when a lower edge of the collar is disposed too deep, such that the collar covers up a part of the trench sidewall along which the buried plate is disposed. Conversely, when the lower edge of the collar is disposed at too high a location and does not contact the buried plate, undesirably high leakage current results.
Therefore, it would be desirable to provide a structure and method of forming a buried plate of a trench capacitor in which the lower edge of the collar is self-aligned to the buried plate.